The present invention relates to strapping connections in integrated circuit memory structures.
Memory devices always comprise at least one cell matrix comprising a plurality of rows, a plurality of columns and, in correspondence with each crossing between the rows and columns, a more or less complex memory cell. The rows and columns consist generally of electrical conductors made of silicide or polysilicon which are materials with relatively low conductivity.
Since memories have ever growing capacities and must meet stringent specifications as regards access time, many manufacturers have elected memory devices where the rows are provided conventionally while the columns are provided of metallic materials having relatively high conductivity and making them from a first metallic layer (metal-1).
To make the devices still faster it has been necessary to reduce the series resistance of the rows. This was conventionally achieved by means of another plurality of electrical conductors running parallel to and superimposed on the conductors of the rows and contacted therewith by means of the opening of VIAs every certain number of memory cells as may be seen in FIG. 1. The conductors of said additional plurality are made of metallic materials having relatively high conductivity and making them from a second metallic layer (metal-2).
The process for making from the second metallic layer the additional plurality of conductors is subject to even larger defects for a variety of reasons, one of the many of which is the difficulty of planarization of the underlying structure. Said defects result in short circuiting of two or more adjacent conductors (depending on the size of the defect, as may be seen in FIG. 1.
It is common practice to obviate said defects by providing redundant rows. In general, redundancy is limited to short circuits between two adjacent rows for reasons of failure frequency and redundancy management circuitry simplicity and, for flash EPROM memories, the space occupied by the row and/or column decoding circuitry.
Indeed, flash EPROM memory devices can be erased only in their entirety while they can be written one cell at a time. If a cell were never written but repeatedly erased (together with the others) it would be "emptied" in a short time and this would lead to read errors for the cells located in the same column. To obviate this shortcoming, before any erasing phase of the device there is a "preconditioning" phase affecting individually all the cells of the device (those of the perfectly operating rows, the defective ones and also the redundant ones) and consisting of writing the cells not already written by injecting charges in the insulated gate of the MOS transistor which makes them up. When a write operation is executed in a row exhibiting a short circuit it is necessary anyway that the cells making it up be actually written so as to avoid future read errors. To do this, stronger and more cumbersome generators are needed in proportion to the stronger current needed to pilot the row despite the short circuit, and this depends on the number of short circuited rows and the size of the defect. Present integration levels do not allow dedicating to said generators a very big area on the chip. Consequently, only short circuits between two adjacent rows are made redundant. The short circuit of multiple rows constitutes an obstacle to operation of the entire device and cannot be accepted nor managed by means of software or firmware avoiding the use of such defective rows (this is naturally true only for flash EPROM memory devices) and hence results in rejection of the device.
This problem is encountered more generally in all the integrated circuits comprising a first plurality of first conductors made of a first relatively low-conductivity material with each having a plurality of first electrical connection points arranged along itself and a second corresponding plurality of second conductors made of a second relatively high-conductivity material with each having a plurality of second electrical connection points arranged along itself and in which said pluralities of first points are electrically connected to said plurality of second points respectively in such a manner as to reduce the series resistance of the first conductors. This is naturally independent of the absolute and mutual arrangement on the integrated circuit, the materials, and the manufacturing process for making the conductors provided this can cause large defects.
The purpose of the present invention is to provide an integrated circuit having a structure such as to be tolerant of large manufacturing defects.
Said purpose is achieved by means of the integrated circuit of the above mentioned type in which strapping connections, formed in an additional thin film layer, each connect two separate locations of a respective one of said word lines to shunt the resistivity of a respective portion of said respective word line; and the strapping connections are arranged, in groups, in a checkerboard pattern over said array. Further advantageous features of the present invention are set forth in the dependent claims.
In accordance with another aspect, the present invention also concerns a memory device where the innovative strapping lines are used to shunt word lines.
By having the second conductors interrupted between some second consecutive points in such a manner as to leave relatively large areas of the integrated circuit not traversed by the second conductors, the probability that a defect would affect two conductors, causing a short circuit between them, is reduced and for three conductors it is reduced even further.
The resulting increase in the series resistance is acceptable in particular for memory devices. Furthermore, thanks to the use of redundant rows for said devices, rejects due to manufacturing defects and in particular those linked to the second metallic layer are practically eliminated.